1 ltc1152 rail-to-rail input rail-to-rail output zero-drift op amp s f ea t u re n input common-mode range includes both rails n output swings rail to rail n output will drive 1k w load n no external components required n input offset voltage: 10 m v max n input offset drift: 100nv/ c max n minimum cmrr: 115db n supply current: 3.0ma max n shutdown pin drops supply current to 5 m a max n output configurable to drive any capacitive load n operates from 2.7v to 14v total supply voltage u s a o pp l ic at i n rail-to-rail amplifiers and buffers n high resolution data acquisition systems n supply current sensing in either rail n low supply voltage transducer amplifiers n high accuracy instrumentation n single negative supply operation d u escriptio the ltc ? 1152 is a high performance, low power zero-drift op amp featuring an input stage that common modes to both power supply rails and an output stage that provides rail-to-rail swing, even into heavy loads. the wide input common-mode range is achieved with a high frequency on-board charge pump. this technique eliminates the crossover distortion and limited cmrr imposed by com- peting technologies. the ltc1152 is a c-load tm of amp, enabling it to drive any capacitive load. the ltc1152 shares the excellent dc performance specs of ltcs other zero-drift amplifiers. typical offset voltage is 1 m v and typical offset drift is 10nv/ c. cmrr and psrr are 130db and 120db and open-loop gain is 130db. input noise voltage is 2 m v p-p from 0.1hz to 10hz. gain-band- width product is 0.7mhz and slew rate is 0.5v/ m s, all with supply current of 3.0ma max over temperature. the ltc1152 also includes a shutdown feature which drops supply current to 1 m a and puts the output stage in a high impedance state. the ltc1152 is available in 8-pin pdip and 8-pin so packages and uses the standard op amp pinout, allowing it to be a plug-in replacement for many standard op amps. 5v 0v 1152 ta02 input and output waveforms rail-to-rail buffer v out 2v/div 0v 5v v in 2v/div u a o pp l ic at i ty p i ca l , ltc and lt are registered trademarks of linear technology corporation. c-load is trademark of linear technology corporation. + out 7 6 4 3 2 ltc1152 5v in 1152 ta01
2 ltc1152 a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio order part number ltc1152cn8 ltc1152cs8 ltc1152in8 ltc1152is8 v s = 5v, t a = operating temperature range, unless otherwise specified. consult factory for military grade parts. 1152 1152i s8 part marking total supply voltage (v + to v C ) ............................. 14v input voltage ............................ v + + 0.3v to v C C 0.3v output short-circuit duration (pin 6) ............. indefinite operating temperature range ltc1152c............................................... 0 c to 70 c ltc1152i .......................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c e lectr ic al c c hara terist ics symbol parameter conditions min typ max units v os input offset voltage t a = 25 c (note 1) 1 10 m v d v os average input offset drift (note 1) l 10 100 nv/ c long-term offset drift 50 nv/ ? mo i b input bias current t a = 25 c (note 2) 10 100 pa l 1000 pa i os input offset current t a = 25 c (note 2) 20 200 pa l 500 pa e n input noise voltage (note 3) r s = 100 w , 0.1hz to 10hz 2 3 m v p-p r s = 100 w , 0.1hz to 1hz 0.5 1 m v p-p i n input noise current f = 10hz 0.6 fa/ ? hz cmrr common-mode rejection ratio v cm = 0v to 5v l 115 130 db psrr power supply rejection ratio v s = 3v to 12v 110 120 db l 105 db a vol large-signal voltage gain r l = 10k, v out = 0.5v to 4.5v l 110 130 db v out maximum output voltage swing (note 4) r l = 1k, v s = single 5v l 4.0 4.4 v r l = 1k, v s = 2.5v l 2.0 2.2 v r l = 100k, v s = 2.5v 2.49 v sr slew rate r l = 10k, c l = 50pf, v s = 2.5v 0.5 v/ m s gbw gain-bandwidth product r l = 10k, c l = 50pf, v s = 2.5v 0.7 mhz i s supply current no load l 2.2 3.0 ma shutdown = 0v l 15 m a i osd output leakage current shutdown = 0v l 10 100 na v cp charge pump output voltage i cp = 0 7.3 v v il shutdown pin input low voltage 2.5 v v ih shutdown pin input high voltage 4 v i in shutdown pin input current v shdn = 0v l C1 C5 m a f cp internal charge pump frequency t a = 25 c 4.7 mhz f smpl internal sampling frequency t a = 25 c 2.3 khz t jmax = 110 c, q ja = 130 c/ w (n8) t jmax = 110 c, q ja = 200 c/ w (s8) 1
2
3
4 8
7
6
5
top view shdn
in
+in
v cp
v +
out
comp n8 package
8-lead pdip
s8 package
8-lead plastic so
3 ltc1152 v s = 3v, t a = operating temperature range, unless otherwise specified. e lectr ic al c c hara terist ics symbol parameter conditions min typ max units v os input offset voltage t a = 25 c (note 1) 1 10 m v d v os average input offset drift (note 1) l 10 100 nv/ c i b input bias current t a = 25 c (note 2) 5 100 pa l 1000 pa i os input offset current t a = 25 c (note 2) 10 200 pa l 500 pa e n input noise voltage (note 3) r s = 100 w , 0.1hz to 10hz 2 m v p-p r s = 100 w , 0.1hz to 1hz 0.75 m v p-p i n input noise current f = 10hz 0.6 fa/ ? hz cmrr common-mode rejection ratio v cm = 0v to 3v l 130 db a vol large-signal voltage gain r l = 10k, v out = 0.5v to 2.5v l 106 130 db v out maximum output voltage swing (note 4) r l = 1k, v s = single 3v l 2.0 2.5 v r l = 100k, v s = 1.5v 1.48 v sr slew rate r l = 10k, c l = 50pf, v s = 1.5v 0.4 v/ m s gbw gain-bandwidth product r l = 10k, c l = 50pf, v s = 1.5v 0.5 mhz i s supply current no load l 1.8 2.5 ma shutdown = 0v l 15 m a i osd output leakage current shutdown = 0v l 10 na v cp charge pump output voltage i cp = 0 4.5 v v il shutdown pin input low voltage 1.2 v v ih shutdown pin input high voltage 2.3 v i in shutdown pin input current v shdn = 0v C 1 m a f cp internal charge pump frequency t a = 25 c 4.2 mhz f smpl internal sampling frequency t a = 25 c 2.1 khz filter at 0.1hz. contact ltc factory for sample tested or 100% tested noise parts. note 4: all output swing measurements are taken with the load resistor connected from output to ground. for single supply tests, only the positive swing is specified (negative swing will be 0v due to the pull-down effect of the load resistor). for dual supply operation, both positive and negative swing are specified. the l denotes specifications which apply over the full operating temperature range. note 1: these parameters are guaranteed by design. thermocouple effects preclude measurement of these voltage levels during automated testing. note 2: at t 0 c these parameters are guaranteed by design and not tested. note 3: 0.1hz to 10hz noise is specified dc coupled in a 10-sec window; 0.1hz to 1hz noise is specified in a 100-sec window with an rc highpass
4 ltc1152 typical perfor m a n ce characteristics uw power supply voltage ( v) 12 common-mode range limit (v) 35 4 6 7 1152 g01 8
6
4
2
0
?
?
?
? common-mode range vs supply voltage total supply voltage (v) 02 supply current (ma) 3.0
2.5
2.0
1.5
1.0 4 6810 1152 g02 12 14 t a = 25 c supply current vs supply voltage temperature ( c) 50 ?5 power supply current (ma) 2.0
1.9
1.8
1.7
1.6
1.5
1.4 02550 1152 g03 75 100 v s = 5v output swing vs load resistance load resistance (k w ) 0.2 output swing ( v) 1 5 10 200 1152 g04 0.5 2 20 50 100 6
5
4
3
2
1
0 t a = 25 c v s = single 5v v s = single 3v v s = 2.5v v s = 1.5v total supply voltage (v) 2 output short-circuit current (ma) 40
30
20
10
0 46810 1152 g05 12 14 source sink t a = 25 c output short-circuit current vs supply voltage total supply voltage (v) 2 open-loop output resistance ( w ) 300
250
200
150
100 46810 1152 g06 12 14 t a = 25 c open-loop output resistance vs supply voltage charge pump voltage vs supply voltage charge pump voltage vs load current input bias current vs temperature temperature ( c) ?0 input bias current ( pa) 1000
100
10 25 25 0 50 75 100 1152 g09
v s = 5v supply current vs temperature total supply voltage (v) 2 charge pump voltage, v cp ?v + (v) 3
2
1
0 4 6810 1152 g07 12 14 t a = 25 c load current ( m a) 0 charge pump voltage, v cp ?v + (v) 40 60 100 20 80 120 140 160 1152 g08 3
2
1
0 t a = 25 c
v s = 5v
5 ltc1152 typical perfor m a n ce characteristics uw v s = 2.5v a v = 1 1152 g16 frequency (hz) power supply rejection ratio (db) 80
70
60
50
40
30
20
10
0
?0 10 1k 10k 1m 1152 g14 100 100k +psrr psrr t a = 25 c frequency (khz) 0.01 voltage gain (db) 0.1 1 10 1152 g12 60
50
40
30
20
10
0
10
20
30
?0 phase shift (deg) 180
160
140
120
100
80
60
40
20
0
?0 t a = 25 c
v s = 2.5v
c comp = 0.1 m f phase gain gain and phase shift vs frequency gain and phase shift vs frequency frequency (hz) voltage gain (db) phase shift (deg) 70
60
50
40
30
20
10
0
10
?0 120
100
80
60
40
20
0 1k 100k 1m 10m 1152 g10 10k t a = 25 c
v s = 2.5v
pin 5 = nc phase gain gain and phase shift vs frequency common-mode rejection ratio vs frequency power supply rejection ratio vs frequency 0.1hz to 10hz input noise time (sec) 0 ( m v) 2
1
0
?
? 8 1152 g18 2 4 6 10 voltage noise vs frequency frequency (hz) 150
125
100
75
50
25
0 1 100 1k 10k 1152 g15 10 voltage noise (nv/ ? hz) large-signal transient response v s = 2.5v a v = 1 1152 g17 small-signal transient response frequency (khz) common-mode rejection ratio (db) 110
100
90
80
70
60
50
40
30 0.1 10 100 1000 1152 g13 1 t a = 25 c
v s = 2.5v frequency (hz) voltage gain (db) phase shift (deg) 1k 100k 1m 10m 1152 g11 10k t a = 25 c
v s = 2.5v
c comp = 1000pf phase gain 70
60
50
40
30
20
10
0
10
?0 120
100
80
60
40
20
0
20
40
?0
6 ltc1152 u s a o pp l ic at i wu u i for atio rail-to-rail operation the ltc1152 is a rail-to-rail input common-mode range, rail-to-rail output swing op amp. most cmos op amps, including the entire ltc zero-drift amplifier line, and even a few bipolar op amps, can and do, claim rail-to-rail output swing. one obvious use for such a device is to provide a unity-gain buffer for 0v to 5v signals running from a single 5v power supply. this is not possible with the vast majority of so-called rail-to-rail op amps; although the output can swing to both rails, the negative input (which is connected to the output) will exceed the common-mode input range of the device at some point (generally about 1.5v below the positive supply), opening the feedback loop and causing unpredictable and sometimes bizarre behavior. the ltc1152 is an exception to this rule. it features both rail-to-rail output swing and rail-to-rail input common- mode range (cmr); the input cmr actually extends be- yond either rail by about 0.3v. this allows unity-gain buffer circuits to operate with any input signal within the power supply rails; input signal swing is limited only by the output stage swing into the load. additionally, signals occurring at either rail (power supply current sensing, for example) can be amplified without any special circuitry. internal charge pump the ltc1152 achieves its rail-to-rail input cmr by using a charge pump to generate an internal voltage approxi- mately 2v higher than v + . the input stages of the op amp are run from this higher voltage, making signals at v + appear to be 2v below the front ends power supply (figure 1). the charge pump is contained entirely within the ltc1152; no external components are required. about 100 m v p-p of residual charge pump switching noise will be present on the output of the ltc1152. this feedthrough is at 4.7mhz, higher than the gain-bandwidth of the ltc1152, and will generally not cause any prob- lems. very sensitive applications can reduce this feedthrough by connecting a capacitor from the cp pin (pin 8) to v + (pin 7); a 0.1 m f capacitor will reduce charge pump feedthrough to negligible levels. the ltc1152 in- cludes an internal diode from pin 8 to pin 7 to prevent external parasitic capacitance from lengthening start-up + out output
rail to rail input 0.1 m f* *optional external
capacitor to reduce
charge pump feedthrough v cc + 2v v cc
(pin 7) cp (pin 8) +in ?n 1152 f01 internal
charge
pump figure 1. ltc1152 internal block diagram time. this diode can stand short-term peak currents of about 50ma, allowing it to quickly charge external capaci- tance to ground or v C . large capacitors (>1 m f) should not be connected between pin 8 and ground or v C to prevent excessive diode current from flowing at start-up. the ltc1152 can withstand continuous short circuits be- tween pin 8 and v + ; however, short circuiting pin 8 to ground or v C will cause large amounts of current to flow through the diode, destroying the ltc1152. dont do it. output drive the ltc1152 features an enhanced output stage that can sink and source 10ma with a single 5v supply while maintaining rail-to-rail output swing under most loading conditions. the output stage can be modeled as a perfect rail-to-rail voltage source with a resistor in series with it; this open-loop output resistance limits the output swing by creating a resistor divider with the output load. the output resistance drops as total power supply voltage increases, as shown in the typical performance curves. it is typically 140 w with a single 5v supply, allowing a 4.4v output swing into a 1k resistor with a single 5v supply. out (pin 6) ? 140 w at 5v supply ltc1152
output
driver v cc (pin 7) r load r out 1152 f02 figure 2. ltc1152 output resistance model
7 ltc1152 compensation/bandwidth limiting the ltc1152 is unity-gain stable with capacitive loads up to 1000pf. larger capacitive loads can be driven by externally compensating the ltc1152. adding 1000pf between comp (pin 5) and out (pin 6) allows capacitive loading of up to 1 m f; 0.1 m f between pins 5 and 6 allows the ltc1152 to drive infinite capacitive load (figure 3). 1
2
3
4 8
7
6
5
c c output *optional diodes to prevent
latch-up with c c > 1 m f 1n4148* 1152 f03 1n4148* ltc1152 v v + figure 3. output compensation connection large compensation capacitors can also be used to limit the bandwidth of the ltc1152. with 0.1 m f from pin 5 to pin 6, the ltc1152s gain-bandwidth product is reduced from 700khz to around 200hz. note that compensation capacitors greater than 1 m f can cause latch-up under severe output fault conditions; this can be prevented by clamping pin 5 to each supply with standard signal diodes, as shown in figure 3. shutdown the ltc1152 includes a shutdown pin (pin 1). when this pin is at v + , the ltc1152 operates normally. an internal 1 m a pull-up keeps the pin high if it is left floating. when pin 1 is pulled low, the part enters shutdown mode; supply current drops to 1 m a, all internal clocking stops and the output enters a high impedance state. during shutdown the voltage at the cp pin (pin 8) will drop to 0.5v below v + . when pin 1 is brought high again, about 10 m s will elapse before the charge pump regains full voltage. during this time the ltc1152 will operate normally, but the input cmr may not include v + . pin 1 is compatible with cmos logic running from the same supply as the ltc1152. addition- ally, the input trip levels allow ground referenced cmos logic signals to interface directly to pin 1 when the ltc1152 is running from 5v or 3v supplies. the internal 1 m a pull-up also allows pin 1 to interface with open-collector/ open-drain devices or discrete transistors. the high impedance output in shutdown allows several ltc1152s to be connected together as a mux, with their outputs tied in parallel and the active channel selected by using the shutdown pins. deselected (shutdown) chan- nels will go to high impedance at the outputs, preventing them from fighting with the active channel. this works best when the individual ltc1152s are connected in noninverting feedback configurations to prevent the feed- back resistors from passing signals through deselected channels. see the typical applications section for a circuit example. zero-drift operation the ltc1152 is a zero-drift op amp. like other ltc zero- drift op amps, it features virtually error-free dc perfor- mance, very little drift over time and temperature, and very low noise at low frequencies. the internal nulling clock runs at about 2.3khz (the charge pump frequency of 4.7mhz divided by 2048) and is synchronized to the internal charge pump to prevent beat frequencies from appearing at the output. the self-nulling circuit constantly corrects the input offset voltage, keeping it typically below 1 m v over the entire input common-mode range. this has the added benefit of providing exceptional cmrr and psrr at low frequenciesCCfar better than competing rail- to-rail op amps. because it uses a sampling front end, the ltc1152 will exhibit aliasing behavior and clock noise at frequencies near the internal 2.3khz sampling frequency. the ltc1152 includes an internal anti-aliasing circuit to keep these error terms to a minimum. as a rule, alias frequencies will be down by (80db C a clg ) in most standard amplifier con- figurations, where a clg is the closed-loop gain of the ltc1152 circuit. clock noise is also dependent on closed- loop gain; it will generally consist of spikes of about 100 m v in amplitude, input referred. in general, these error terms are too small to affect most applications. for a more detailed explanation of zero-drift amplifier behavior, see the ltc1051/ltc1053 data sheet. u s a o pp l ic at i wu u i for atio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
8 ltc1152 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 ? linear technology corporation 1995 lt/gp 0195 10k ? printed in usa u s a o pp l ic at i wu u i for atio high gain amplifier with 1.5v supplies out 1.5v 1.5v a v = 10k
= 80db 10 w 0.1 m f ltc1152 2 3 7 6 4 + in 1152 ta03 100k high precision three-input mux sel1 out sel2 sel3 select inputs are cmos logic compatible.
select only one channel at once! 1.1k ltc1152 2 3 1 6 in 1
a v = 10 ltc1152 2 3 1 6 in 2
a v = 1000 ltc1152 2 3 1 6 in 3
a v = 1 1152 ta04 10k 10 w 10k + + + high-side power supply current sensing package descriptio n u dimensions in inches (millimeters) unless otherwise noted. n8 package 8-lead plastic dip out
1v/100ma
load current in
measured circuit gnd to
measured
circuit 5v gnd 0.01 w 100 w 0.1 m f 0.1 m f ltc1152 3 2 2 3 6 + lt1097 6 + 1152 ta05 100k 10k 10k 10k 10k change sense resistor
to change sensitivity n8 0694 0.045 0.015
(1.143 0.381) 0.100 0.010
(2.540 0.254) 0.065
(1.651)
typ 0.045 ?0.065
(1.143 ?1.651) 0.130 0.005
(3.302 0.127) 0.015
(0.380)
min 0.018 0.003
(0.457 0.076) 0.125
(3.175)
min
0.009 ?0.015
(0.229 ?0.381) 0.300 ?0.325
(7.620 ?8.255) 0.325 +0.025
0.015 +0.635
0.381 8.255 () 12 3 4 87 6 5 0.255 0.015*
(6.477 0.381)
0.400*
(10.160)
max *these dimensions do not include
mold flash or protrusions.
mold flash or protursions shall
not exceed 0.010 inch (0.254mm). s8 package 8-lead plastic soic 1 2 3 4 0.150 ?0.157*
(3.810 ?3.988) 8 7 6 5 0.189 ?0.197*
(4.801 ?5.004) 0.228 ?0.244
(5.791 ?6.197) so8 0294 0.053 ?0.069
(1.346 ?1.752) 0.014 ?0.019
(0.355 ?0.483) 0.004 ?0.010
(0.101 ?0.254) 0.050
(1.270)
bsc 0.016 ?0.050
0.406 ?1.270 0.010 ?0.020
(0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010
(0.203 ?0.254) *these dimensions do not include
mold flash or protrusions.
mold flash or protrusions shall
not exceed 0.006 inch (0.15mm).
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